#include "p24FJ64GA004.h"

//See below for description of FUSED parameters
_CONFIG1(FWDTEN_OFF & ICS_PGx2 & COE_ON & BKBUG_ON & GWRP_OFF & GCP_OFF & JTAGEN_OFF)

//See below for description of FUSED parameters
_CONFIG2(POSCMOD_NONE & I2C1SEL_PRI & IOL1WAY_ON & OSCIOFNC_ON & FCKSM_CSDCMD & FNOSC_FRCPLL & SOSCSEL_SOSC & WUTSEL_FST & IESO_OFF)

/*
** Only one invocation of CONFIG1 should appear in a project,
** at the top of a C source file (outside of any function).
**
** The following constants can be used to set CONFIG1.
** Multiple options may be combined, as shown:
**
** _CONFIG1( OPT1_ON & OPT2_OFF & OPT3_PLL )
**
**   Watchdog Timer Postscaler:
**     WDTPS_PS1            1:1
**     WDTPS_PS2            1:2
**     WDTPS_PS4            1:4
**     WDTPS_PS8            1:8
**     WDTPS_PS16           1:16
**     WDTPS_PS32           1:32
**     WDTPS_PS64           1:64
**     WDTPS_PS128          1:128
**     WDTPS_PS256          1:256
**     WDTPS_PS512          1:512
**     WDTPS_PS1024         1:1,024
**     WDTPS_PS2048         1:2,048
**     WDTPS_PS4096         1:4,096
**     WDTPS_PS8192         1:8,192
**     WDTPS_PS16384        1:16,384
**     WDTPS_PS32768        1:32,768
**
**   WDT Prescaler:
**     FWPSA_PR32           Prescaler ratio of 1:128
**     FWPSA_PR128          Prescaler ratio of 1:32
**
**   Watchdog Timer Window:
**     WINDIS_OFF           Windowed Watchdog Timer enabled; FWDTEN must be 1
**     WINDIS_ON            Standard Watchdog Timer enabled,(Windowed-mode is disabled)
**
**   Watchdog Timer Enable:
**     FWDTEN_OFF           Watchdog Timer is disabled
**     FWDTEN_ON            Watchdog Timer is enabled
**
**   Comm Channel Select:
**     ICS_PGx3             Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3
**     ICS_PGx2             Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2
**     ICS_PGx1             Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1
**
**   Set Clip On Emulation Mode:
**     COE_ON               Reset Into Clip On Emulation Mode
**     COE_OFF              Reset Into Operational Mode
**
**   Background Debug:
**     BKBUG_ON             Device resets into Debug mode
**     BKBUG_OFF            Device resets into Operational mode
**
**   General Code Segment Write Protect:
**     GWRP_ON              Writes to program memory are disabled
**     GWRP_OFF             Writes to program memory are allowed
**
**   General Code Segment Code Protect:
**     GCP_ON               Code protection is enabled for the entire program memory space
**     GCP_OFF              Code protection is disabled
**
**   JTAG Port Enable:
**     JTAGEN_OFF           JTAG port is disabled
**     JTAGEN_ON            JTAG port is enabled
**
*/

/*
** Only one invocation of CONFIG2 should appear in a project,
** at the top of a C source file (outside of any function).
**
** The following constants can be used to set CONFIG2.
** Multiple options may be combined, as shown:
**
** _CONFIG2( OPT1_ON & OPT2_OFF & OPT3_PLL )
**
**   Primary Oscillator Select:
**     POSCMOD_EC           EC Oscillator mode selected
**     POSCMOD_XT           XT Oscillator mode selected
**     POSCMOD_HS           HS Oscillator mode selected
**     POSCMOD_NONE         Primary oscillator disabled
**
**   I2C1 Pin Location Select:
**     I2C1SEL_SEC          Use alternate SCL1/SDA1 pins
**     I2C1SEL_PRI          Use default SCL1/SDA1 pins
**
**   IOLOCK Protection:
**     IOL1WAY_OFF          IOLOCK may be changed via unlocking seq
**     IOL1WAY_ON           Once IOLOCK is set, cannot be changed
**
**   Primary Oscillator Output Function:
**     OSCIOFNC_ON          OSC2/CLKO/RC15 functions as port I/O (RC15)
**     OSCIOFNC_OFF         OSC2/CLKO/RC15 functions as CLKO (FOSC/2)
**
**   Clock Switching and Monitor:
**     FCKSM_CSECME         Clock switching is enabled, Fail-Safe Clock Monitor is enabled
**     FCKSM_CSECMD         Clock switching is enabled, Fail-Safe Clock Monitor is disabled
**     FCKSM_CSDCMD         Clock switching and Fail-Safe Clock Monitor are disabled
**
**   Oscillator Select:
**     FNOSC_FRC            Fast RC Oscillator (FRC)
**     FNOSC_FRCPLL         Fast RC Oscillator with PLL module (FRCPLL)
**     FNOSC_PRI            Primary Oscillator (XT, HS, EC)
**     FNOSC_PRIPLL         Primary Oscillator with PLL module (HSPLL, ECPLL)
**     FNOSC_SOSC           Secondary Oscillator (SOSC)
**     FNOSC_LPRC           Low-Power RC Oscillator (LPRC)
**     FNOSC_FRCDIV         Fast RC Oscillator with Postscaler (FRCDIV)
**
**   Sec Oscillator Select:
**     SOSCSEL_LPSOSC       Low Power Secondary Oscillator (LPSOSC)
**     SOSCSEL_SOSC         Default Secondary Oscillator (SOSC)
**
**   Wake-up timer Select:
**     WUTSEL_FST           Fast Wake-up Timer
**     WUTSEL_LEG           Legacy Wake-up Timer
**
**   Internal External Switch Over Mode:
**     IESO_OFF             IESO mode (Two-Speed Start-up) disabled
**     IESO_ON              IESO mode (Two-Speed Start-up) enabled
**
*/

#include "hardware_Init.h"

/*
 * Setup the processor ready for the demo.
 */
void setupHardware( void )
{
	
/*
Configure the Oscillator
*/
	/*OSCCON (Oscillator control Register)*/
		_COSC 		= 1;	//Current Oscillator Selection bits
							//		111 = Fast RC Oscillator with Postscaler (FRCDIV)
							//		110 = Reserved
							//		101 = Low-Power RC Oscillator (LPRC)
							//		100 = Secondary Oscillator (SOSC)
							//		011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
							//		010 = Primary Oscillator (XT, HS, EC)
							//		001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
							//		000 = Fast RC Oscillator (FRC)
	
		_NOSC 		= 1;	//New Oscillator Selection bits(1)
							//		111 = Fast RC Oscillator with Postscaler (FRCDIV)
							//		110 = Reserved
							//		101 = Low-Power RC Oscillator (LPRC)
							//		100 = Secondary Oscillator (SOSC)
							//		011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
							//		010 = Primary Oscillator (XT, HS, EC)
							//		001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
							//		000 = Fast RC Oscillator (FRC)
		_CLKLOCK 	= 1;	//Clock Selection Lock Enabled bit
							//		If FSCM is enabled (FCKSM1 = 1):
							//			1 = Clock and PLL selections are locked
							//			0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
							//		If FSCM is disabled (FCKSM1 = 0):
							//			Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
		_IOLOCK 	= 0;	//I/O Lock Enable bit(2)
							//		1 = I/O lock is active
							//		0 = I/O lock is not active
		_SOSCEN 	= 0;	//32 kHz Secondary Oscillator (SOSC) Enable bit
							//		1 = Enable secondary oscillator
							//		0 = Disable secondary oscillator

	/*CLKDIV: (CLOCK DIVIDER REGISTER)*/
		_ROI		= 0;	//Recover on Interrupt bit
							//		1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
							//		0 = Interrupts have no effect on the DOZEN bit
		_DOZE 		= 0;	//CPU Peripheral Clock Ratio Select bits
							//		111 = 1:128
							//		110 = 1:64
							//		101 = 1:32
							//		100 = 1:16
							//		011 = 1:8
							//		010 = 1:4
							//		001 = 1:2
							//		000 = 1:1
		_DOZEN 		= 0;	//DOZE Enable bit(1)
							//		1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio
							//		0 = CPU peripheral clock ratio set to 1:1
		_RCDIV 		= 0;	//FRC Postscaler Select bits
							//		111 = 31.25 kHz (divide by 256)
							//		110 = 125 kHz (divide by 64)
							//		101 = 250 kHz (divide by 32)
							//		100 = 500 kHz (divide by 16)
							//		011 = 1 MHz (divide by 8)
							//		010 = 2 MHz (divide by 4)
							//		001 = 4 MHz (divide by 2)
							//		000 = 8 MHz (divide by 1)
}
